The present invention relates in general to semiconductor technology, and more particularly, to a structure and method for forming a salicide on the gate electrode of a trench-gate field effect transistor (FET).
Conventional metal-oxide-semiconductor (MOS) integrated circuits often utilize a low resistance titanium silicide layer on the polysilicon gate electrode to reduce gate resistance. The titanium silicide layer is generally formed using a self-aligned process. A thin layer of titanium is deposited on the wafer and the wafer is heated. The titanium reacts with exposed silicon to form a titanium silicide. Areas not exposed to silicon do not react, and the un-reacted titanium is removed during subsequent cleaning processes. A silicide formed by such a process may be referred to as a salicide, which is a term used in the art to refer to a self-aligned silicide.
Conventional MOS integrated circuits utilizing a titanium salicide layer require spacers. The spacers provide a physical and electrical barrier between the titanium salicide and nearby conductive layers to prevent shorting and bridging. In a conventional trench-gate FET, spacers are formed adjacent to the gate dielectric along the trench sidewalls to isolate the titanium salicide from the source regions. Without spacers, the titanium used to form titanium salicide can react with the silicon in the gate dielectric to form titanium silicide stringers that cause shorting between the titanium salicide and the source regions. Also, titanium salicide growth is isotropic, and the salicide layer can extend laterally causing bridging.
Using spacers, however, reduces the cross-sectional area of the salicide layer thus increasing gate resistance. Also, with trench-gate FETs the dielectric layer covering mesa surfaces adjacent to the trench is typically removed during spacer etch, thus allowing salicide to form on the mesa surfaces. Salicide formed on the mesa surfaces is difficult to remove thus impacting subsequent contact etch processes.
Thus, there is a general need for improved structures and methods for forming a salicide on the gate electrode of a trench-gate FET.